A high-performance energy-efficient 75.17 dB two-stage operational amplifier

Abstract

This paper discusses the design and analysis of two-stage CMOS operational amplifier. This design is operated at the supply of 1.5 V in 90 nm CMOS technology. In this design, 75.17 dB open-loop gain is achieved and having 7.73 MHz unity gain bandwidth and 148.8 m degree phase margin. This circuit has 10 pF capacitive load with 0.14 nW average power dissipation and slew rate is 0.25 V/μs. This proposed circuit is designed and simulated in cadence UMC 90 nm technology.