MEASUREMENT OF INTERFACE DEFECT STATES AT OXIDIZED SILICON SURFACES BY CONSTANT-CAPACITANCE DLTS.

Abstract

The interface-state distribution for the as-oxidized surface on single-crystal silicon is dominated by a broad peak centered approximately 0. 3 eV above the Si valence-band maximum. Theoretical studies have suggested that this peak is due to a trivalent silicon defect at the Si-SiO//2 interface. Constant-capacitance DLTS and the quasistatic capacitance-voltage technique are used to characterize this defect on (100)- and (111)-oriented silicon surfaces. It is shown that: (1) the characteristic defect is present at the Si-SiO//2 interface on both n-type and p-type silicon, (2) the density of the defect is higher on (111)-oriented than on (100)-oriented silicon for identically prepared specimens, and (3) the defect density can be reduced by a high-temperature, postoxidation anneal in either an argon or nitrogen ambient.