Syllogistic reasoning is modeled in analog hardware and some hardware models, i.e. syllogisms Baroco and Darii are presented. Chaining of syllogisms is modeled by using original min-max entities (circuits), "to see" whether the two rules, modeled in dedicated hardware, i.e., IF A THEN B and IF B THEN C imply the "hardware" rule IF A THEN C. The preliminaries include original min-max circuits based on operational amplifiers (Op-Amp), straight lines Op-Amp generators and different test circuits designed in Electronics WorkBench simulation environment and in real hardware. The "stage" to perform modeling is the phase plane. © 2012 IFIP International Federation for Information Processing.
CITATION STYLE
Kovacevic, D., Pribacic, N., Antonic, R., Kovacevic, A., & Jovic, M. (2012). Modeling of syllogisms in analog hardware. In IFIP Advances in Information and Communication Technology (Vol. 381 AICT, pp. 443–452). https://doi.org/10.1007/978-3-642-33409-2_46
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