Performance analysis of TEA block cipher for low power applications

Abstract

The FPGA based embedded system plays a vital role in the implementation of many cryptographic applications especially in the field of wireless communication. The security constraint applications increasingly demand the encryption process for sensitive data transfer from one end to the other end. The software implementation of security algorithms are easy to implement but it lags in its execution speed and performance. Therefore, hardware implementations are considered to be a good alternate, since they provide additive performance along with the low power and less memory consumption. The Tiny Encryption Algorithm (TEA) is one of the fastest and efficient cryptographic algorithms well suited for many real time data communications with moderate security. This paper analyzes the hardware implementation of TEA in FPGA with different approaches that consumes lesser resources with increased execution speed. This work emphasizes the efficient implementation of TEA algorithm for various applications where the hardware resources are limited and power constraints are stringent. © 2012 Springer-Verlag.