FPGA-based redundancy bits reduction algorithm using the enhanced error detection correction code

Abstract

To ensure an error-free transmission in packet switching, additional check bits (either header or a payload) are typically appended to the input data of a message for error detection especially in a string of binary code. Normally, it comes from the input message and as a result of a deterministic algorithm after these data have been processed. The receiver system implements the said algorithm, while the transmitter used it to match the reliability of the sent information and detects whether an error bit has occurred or not. The corrupted bits will be corrected, recovered, and matched with the original message. To further improve the detection and correction of the corrupted transmitted bits, an enhanced error detection correction code implementation was proposed and developed in this paper. This will improve the limitations of using cyclic redundancy checking (CRC) code and Hamming code, by reducing the number of the redundancy bits 'r' in CRC due to the needed polynomial generator, and the overhead of interspersing of the r in conventional Hamming code, respectively. Xilinx Spartan 6 (XC7Z020-2CLG4841) FPGA was used to synthesize the proposed enhanced error detection code (EEDC) method. Based on the results, the transmission rate is faster, and an increase in detection of random errors compared with using CRC and Hamming codes.