Pipelining architecture of AES encryption and key generation with search based memory

Abstract

A high speed security algorithm is always important for wired/wireless environment. The symmetric block cipher plays a major role in the bulk data encryption. One of the best existing symmetric security algorithms to provide data security is AES. AES has the advantage of being implemented in both hardware and software. We implement the AES in hardware because the hardware implementation has the advantage of increased throughput and offers better security. In order to reduce the constraint on the hardware resources while implementing the look-up table based s-box we propose a search based s-box architecture. Also the pipelined architecture of the AES algorithm is used in order to increase the throughput of the algorithm. The key schedule algorithm of the AES encryption is also pipelined. © 2010 Springer-Verlag Berlin Heidelberg.