Stacked-FET linear SOI CMOS SPDT antenna switch with input P1dB greater than 40dBm

Abstract

The power handling capability is the most stringent specification for antenna switches, and this is dominated by a significant amount of leakage current of off-state FETs. For achieving maximum power handling capability of antenna switches, new DC I-V (FFI-V) characterization method to characterize RF P1dB point of off-state FETs is proposed and experimental study on optimum DC gate and body bias is performed based on proposed FFI-V method. Using Ron and Coff of minimum channel length MOSFETs at aforementioned optimum DC bias point, antenna switch design methodology for maximum power handling capability and minimum insertion loss is established. The designed SOI CMOS SPDT antenna switch integrated with switch controller shows insertion loss less than 0.5 dB and input P1dB greater than +40 dBm.