Abstract
Dynamically trace scheduled VLIW (DTSVLIW) architectures can be used to implement machines that execute code of current RISC or CISC instruction set architectures in a VLIW fashion, delivering instruction level parallelism (ILP) with backward code compatibility. This paper presents the effect of multicycle instructions on the performance of a DTSVLIW architecture running the SPECint95 benchmarks.
Cite
CITATION STYLE
De Souza, A. F., & Rounce, P. (1999). Effect of multicycle instructions on the integer performance of the dynamically trace scheduled VLIW architecture. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 1593, pp. 1203–1206). Springer Verlag. https://doi.org/10.1007/bfb0100690
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