Rules for Analog and Mixed-Signal VHDL-AMS Modeling

Abstract

Since the standardization in 1999 the hardware description language VHDL-AMS is widely used for the modeling of digital, analog, and mixed-signal systems. On the one hand, the powerful language constructs allow a very flexible creation of user-defined models. On the other hand, it is possible to define simulation problems with correct syntax but without a solution. From a mathematical point of view some reasons of such problems are discussed and rules are established that may help to avoid these difficulties