Several techniques to simulate dynamically reconfigurable logic (DRL) have been published during the last decade. These methods each have their own strengths and weaknesses, and perform well when used under particular circumstances. This paper introduces a revised version of dynamic circuit switching (DCS), a DRL simulation technique reported previously, which improves the accuracy of the simulation models and extends the range of situations to which they can be applied. The internal state of dynamic tasks that contain memory elements can change when they are reconfigured. Modelling this presents a further simulation requirement. The paper indicates how this can be achieved by including the ideas behind another simulation technique, clock morphing, in the methodology. Finally, the run-time overheads introduced by the technique are analysed. © Springer-Verlag Berlin Heidelberg 2002.
CITATION STYLE
Robertson, I., Irvine, J., Lysaght, P., & Robinson, D. (2002). Improved functional simulation of dynamically reconfigurable logic. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 2438 LNCS, pp. 152–161). Springer Verlag. https://doi.org/10.1007/3-540-46117-5_17
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