Low-Power design techniques and test implications

Abstract

This chapter provides a brief overview of the prevalent design techniques for dynamic and leakage power reduction in both logic and memory circuits. It also provides an introduction to power specification format, which allows specification of circuit properties with respect to power dissipation in a consistent manner. Next, it discusses the impact of existing low-power design techniques on test. Finally, it covers the test implications of the post-silicon adaptation approaches for power reduction. © 2010 Springer-Verlag US.