Cost-effective buffered wormhole routing

Abstract

The cost-effectiveness of wormhole torus-networks is systematically evaluated with emphasis on new buffered-wormhole routing algorithms. These algorithms use hardwired datelines and escape channels to alleviate bottleneck and bubble problems caused by previous algorithms and so to improve the buffer efficiency with little hardware overhead. A two-part evaluation environment is developed consisting of a cycle-driven simulator for high-level measurements such as network capacity and an ASIC design package for low-level measurements such as operating frequency and chip area. This environment is used to demonstrate that the new routers are more cost-effective than their counterparts under various workload parameters. © Springer-Verlag Berlin Heidelberg 2004.