A study on test case generation based on state diagram in modeling and simulation environment

Abstract

In the conventional tests, test case is generated in the design stage. However, actual test can be executed after its embodiment. As there is as much time difference between the design and execution of the test, the errors in the designs of test and software are checked out late. This paper is proposing the test case generation method so as automatic test can be carried out in the virtual simulation environment. The method proposed generates the test case automatically based on the state diagram and executes it in the virtual simulator. It can reduce the time difference between the design and execution of test, accordingly, to find out the error in the test case and problems in the design promptly. As a result, it can identify the error in the beginning stage of software development and save the time and expense need for the development. © 2011 Springer-Verlag Berlin Heidelberg.