Systematic security assessment at an early processor design stage

Abstract

One critical aspect of a secure hardware design is the ability to measure a design's security. In this paper, we propose a hardware security assessment scheme that provides a systematic way of measuring and categorizing a hardware feature's security concern at an early design stage. The proposed scheme is developed to measure security exposure and risk of a design. The scheme takes a two level questionnaire format and scores a feature based on the answers to the questions. Based on the security score, a feature is then categorized into no, low, medium or high security concern. We discuss several representative questions in detail and evaluate a number of current and future processor features using the scheme. Overall, the assessments from our scheme concur with the security evaluation results by industry security experts, providing an effective security measurement for hardware designs. © 2011 Springer-Verlag.