QCA Based Error Detection Circuit for Nano Communication Network

Abstract

This paper outlines low power nano-scale circuit design for even parity generator, as well as, even parity checker circuit using quantum-dot cellular automata (QCA). The proposed even parity generator and even parity checker are achieved by using a new layout of XOR gate. This new XOR gate as a state-of-the-art is much denser and faster than the existing ones. The proposed parity generator has outshined the existing design by reducing the cell count as 10%, area as 5.66%, and latency by 12.5%. The proposed parity checker has also outshined the existing design with an improvement in cell count as 17.94% and in the area as 38.46% having a reduction in latency of 22.22%. The comparison proves that the circuits are denser and faster than the existing one. Nano communication architecture with the proposed circuits also demonstrates the efficiency of this design. Furthermore, the bit-error coverage by the proposed method is described. Besides, the defects in the circuits are explored to facilitate guide to proper implementation. The tests vectors are proposed to identify the defects in the designs and the defect coverage by those test vectors. The estimation of dissipated energy by the layouts establishes a very low energy dissipation nature of the designs. Different parameters like a logic gate, density, and latency are utilized to evaluate the proposed designs that confirm the faster processing speed at nano-scale.