This paper presents a description of an architecture of an EIT hardware for research. Both, hardware and software for capturing and processing of the EIT signals are addressed. The system is divided in modules with defined requirements and connections, therefore, different implementations are possible. Details of an implementation conceived to validate the architecture with respect to processing speed is also described.
CITATION STYLE
Lima, R. G., Dos Santos, A. L., De Camargo, E. D. L. B., De Moura, F. S., & Santos, T. B. R. (2016). Signal processing architecture for electrical tomography impedance. In IFMBE Proceedings (Vol. 54, pp. 64–67). Springer Verlag. https://doi.org/10.1007/978-981-287-928-8_17
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