An incremental verification paradigm for embedded systems

Abstract

Embedded Systems complexity is enhancing many folds in most of the product domains. Changing requirements and uncertainty during early stages of development are of greatest concern for the developing community, as they enhance system development complexities. Verification encompasses all aspects of system development process. This paper proposes an incremental paradigm that incorporates early integration and reduces uncertainty during initial phases of development under changing conditions of requirements. The method can be represented by a cascaded V-model. The verification methodology implementation issues are presented.