Today, reconfgurable spatial architectures (RSAs) have sprung up as accelerators for compute-and data-intensive domains because they deliver energy and area efciency close to ASICs and still retain sufcient programmability to keep the development cost low. The mapper, which is responsible for mapping algorithms onto RSAs, favors a systematic backtracking methodology because of high portability for evolving RSA designs. However, exponentially scaling compilation time has become the major obstacle. The key observation of this paper is that the key limiting factor to the systematic backtracking mappers is the waterfall mapping model which resolves all mapping variables and constraints at the same time using single-level intermediate representations (IRs). This work proposes CaSMap, an agile mapper framework independent of software and hardware of RSAs. By clustering the lowest-level software and hardware IRs into multi-level IRs, the original mapping process can be scattered as multi-stage decomposed ones and therefore the mapping problem with exponential complexity is mitigated. This paper introduces (a) strategies for clustering low-level hardware and software IRs with static connectivity and critical path analysis. (b) a multi-level scattered mapping model in which the higher-level model carries out the heuristics from IR clustering, endeavors to promote mapping success rate, and reduces the scale of the lower-level model. Our evaluation shows that CaSMap is able to reduce the problem scale (nonzeros) by 80.5% (23.1%-94.9%) and achieve a mapping time speedup of 83× over the state-of-the-art waterfall mapper across four diferent RSA topologies: MorphoSys, HReA, HyCUBE, and REVEL.
CITATION STYLE
Man, X., Zhu, J., Song, G., Yin, S., Wei, S., & Liu, L. (2022). CaSMap: Agile Mapper for Reconfigurable Spatial Architectures by Automatically Clustering Intermediate Representations and Scatering Mapping Process. In Proceedings - International Symposium on Computer Architecture (pp. 259–272). Institute of Electrical and Electronics Engineers Inc. https://doi.org/10.1145/3470496.3527426
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