Electronic design automation for increased robustness in inkjet-printed electronics

Abstract

Printed electronics is of great interest for low-cost, large-area fabrication due to fast and scalable processes with low material consumption. However, notable resources are currently required for fine-tuning layout designs and process parameters to prevent unintended fabrication artifacts. This study proposes the use of electronic design automation to mitigate such artifacts by segmenting input layouts and arranging the resulting objects in separate conflict-free layers. To this end, two exemplary conflicts with relevance for inkjet printing are defined. The first addresses heterogeneous structures composed of low- and high-resolution features. The second is concerned with layouts requiring a high feature density. Experimental data is used to derive constraints for layer arrangement. Finally, mixed-integer-linear programming is used to formally model the problem and minimize the total number of layers under the aforementioned constraints. The results of printing test layouts with and without algorithmic treatment are characterized in terms of film morphology, device functionality, and fabrication yield. The data demonstrates a more consistent fabrication outcome and significantly increased yields for optimized fabrication batches compared to non-optimized ones. The final processing of the layouts requires no human intervention and can readily be transferred to a variety of ink-substrate systems.