Execution latency reduction via variable latency pipeline and instruction reuse

Abstract

Operand bypass logic might be one of the critical structures for future microprocessors to achieve high clock speed. T he delay of the logic imposes the execution time budget to be reduced significantly, resulting in that the execution stage is divided into several stages. V ariable latency pipeline (VLP) structure has the advantages of pipelining and pseudo-asynchronous design techniques. Ac cording to source operands delivered to arithmetic units, the VLP changes execution latency and thus it achieves both high speed and low latency for most of the operands. In this paper we evaluate the VLP on dynamically scheduled superscalar processors using a cycle-by-cycle simulator. O ur experimental results show that the VLP is effective for reducing the effective execution time, and thus the constraints on the operand bypass logic is mitigated. W e also evaluate instruction reuse technique in order to support the VLP.