Efficient post-layout power-delay curve generation

Abstract

We have developed a complete design flow from Verilog/VHDL to layout that generates what is effectively a post-layout power versus delay curve for a digital IC block. Post-layout timing convergence is rapid over the entire delay range spanned by a power versus delay tradeoff curve. The points on the gate-sizing generated power-delay curve, when actually laid out, are extremely close in transistor-level simulated power and delay, using full 3D extracted parasitics. The user can therefore confidently obtain any feasible post-layout power-delay tradeoff from the power-delay curve for a logic block. To the best of our knowledge, this is the first report of such a post-layout capability. © Springer-Verlag Berlin Heidelberg 2005.