Using reconfigurable hardware to speed up product development and performance

Abstract

Harp1 is a circuit board designed to exploit the rigorous compilation of parallel algorithms directly into hardware. It includes a transputer closely-coupled to a Field-Programmable Gate Array (FPGA). The whole system can be regarded as an instance of a process in the theory of Communicating Sequential Processes (CSP). The major elements themselves can also be viewed in the same way: both the transputer and the FPGA can implement many parallel communicating sub-processes. The Harp1 design includes memory banks, a programmable frequency synthesizer and several communication ports. The latter supports the use of parallel arrays of Harp1 boards, as well as interfacing to external hardware. Harp1 is the target of mathematical tools based upon the Ruby and occam languages, which enable unusual and novel applications to be produced and demonstrated correctly and rapidly; the aim is to produce high quality designs at low costs and with reduced development time.