Self-testing of linear segments in user-programmed FPGAs

Abstract

A method for the development of a test plan for BIST-based exhaustive testing of a circuit implemented with an in-system reconfigurable FPGA is presented. A test plan for application-dependent testing of an FPGA is based on the concept of a logic cone and linear segment. Linear segments that satisfy single- or multi-generator compatibility requirement can be combinationally exhaustively tested concurrently and are merged into a test block. Two methods for merging logic cones and linear segments are proposed. Experimental results are presented.