Aspects regarding the implementation of Hsiao code to the cache level of a memory hierarchy with FPGA Xilinx circuits

Abstract

In this paper we will apply a SEC-DED code to the cache level of a memory hierarchy. From the category of SEC-DED (Single Error Correction Double Error Detection) codes we select the Hsiao code. The Hsiao code is a odd-weight-column SEC-DED code. For correction of single-bit error we use a syndrome decoder, a syndrome generator and the check bits generator circuit. © Springer Science+Business Media B.V. 2010.