We propose a new design for an energy-efficient hardware transactional memory (HTM) system for power-aware embedded devices. Prior hardware transactional memory designs proposed a small, fully-associative transactional cache at the same level as the L1 cache. We propose an alternative design that unifies the transactional and L1 caches, and provides a small victim cache to reduce effects of capacity and conflict evictions. We evaluate our new HTM scheme on a variety of benchmarks, both in terms of energy and performance. We show that the victim cache scheme can provide up to a 4X improvement in energy-delay product, compared to a traditional HTM scheme that uses a separate transactional cache. © 2010 Springer-Verlag.
CITATION STYLE
Ferri, C., Wood, S., Moreshet, T., Bahar, I., & Herlihy, M. (2010). Energy and throughput efficient transactional memory for embedded multicore systems. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 5952 LNCS, pp. 50–65). https://doi.org/10.1007/978-3-642-11515-8_6
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