Some design aspects for VLIW architectures exploiting fine—grained parallelism

Abstract

Very Long Instruction Word Architectures (VLIW architectures) can exploit the fine-grained (instruction level) parallelism typically found in sequential-natured program code. A parallelizing compiler is used to restructure the program code. Sophisticated global compaction techniques have emerged that can effectively extract fine-grained parallelism from ordinary sequential natured program code. In this paper we propose an effective mechanism for multiway branches and introduce a generalized conditional execution model for VLIW architectures. For the evaluation of VLIW architectures and their parallelizing compilers we use a simulation environment. This simulation environment comprises a parallelizing compiler and a highly configurable simulator for VLIW architectures. With this simulation environment the architectural enhancements proposed in this paper can be evaluated. Our studies are directed in finding high performance combinations of VLIW architectures and parallelizing compilers.