Abstract
The paper presents high-level modelling and formal analysis and verification on an FPGA-based multigigabit network monitoring system called Scampi. UPPAAL was applied in this work to establish some correctness and throughput results on a model intentionally built using patterns reusable in other similar projects. Some initial experiments with parametric analysis using TREX were performed too. © IFIP International Federation for Information Processing 2005.
Cite
CITATION STYLE
Matoušek, P., Smrčka, A., & Vojnar, T. (2005). High-level modelling, analysis, and verification on FPGA-Based hardware design. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 3725 LNCS, pp. 371–375). Springer Verlag. https://doi.org/10.1007/11560548_34
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