Dynamic scheduling of pipelined functional units in coarse-grained reconfigurable array elements

Abstract

Coarse-Grained Reconfigurable Arrays (CGRAs) promise higher computing power and better energy efficiency than field programmable gate arrays (FPGAs). Thus, they are attractive not only for embedded applications, but also for high-performance computing (HPC). Yet, in such applications floating point (FP) operations are the main workload. Most of the previous research on CGRAs considered only operations on integral data types, which can be executed in one clock cycle. In contrast, FP operations take multiple clock cycles and different operations have different latencies. In this contribution, we present a new mechanism that resolves data and structural hazards in processing elements (PEs) that feature in-order issue, but out-of-order completion of operations. We show that our mechanism is more area efficient than scoreboarding in most of the relevant cases. In addition, our mechanism is universal, i.e. not only restricted to PEs in CGRAs, but also applicable to microprocessors.