Abstract
A new systolic serial-parallel scheme that implements the Montgomery multiplier is presented. The serial input of this multiplier consists of two sets of data that enter in a bit-interleaved form. The results are also derived in the same form. The design, with minor modifications, can be used for the implementation of the RSA algorithm. The circuit yields low hardware complexity and permits high-speed operation with 100% efficiency.
Cite
CITATION STYLE
Moshopoulos, N. K., & Pekmestzi, K. Z. (2001). A novel systolic architecture for an efficient RSA implementation. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 1992, pp. 416–421). Springer Verlag. https://doi.org/10.1007/3-540-44586-2_30
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