Physical design and implementation of 3D tree-based FPGAs

Abstract

The semiconductor industries current enthusiasm for 3D-ICs is widespread and well warranted, but designing those 3D devices presents a challenge. Normal 2D design tools are thoroughly honed and refined over many years, nonetheless fail to address some of the critical issues of 3D-IC design. A new 3D-IC design process is evolving gradually from the 2D heritage. Today there are tools to handle a complete back-end flow and strides are being made to enable true 3D design and implementation using TSVs. In this chapter we discuss the design algorithms and techniques to develop 3D physical design tools and use of these tools to design and fabricate 3D stacked Tree-based FPGAs. This chapter starts with development of VHDL code generator and continue to the development 3D layouts of Tree-based FPGA using the 3D physical design tools developed for 3D FPGA design. A new CAD tool set for 3D physical design and verification based on Global Foundries 130nm technology node modified to use Tezzaron’s TSV technology is also developed and presented in this chapter. Through this chapter we addressed few specific issues 3D designers often encounter dealing with tools that are not specifically designed to meet their needs. We also presented few additional 3D design support tools such as 3D LVS/DRC to verify the LVS of the partitioned and merged 3D designs.