The LTL model checker that we use provides sound decomposition mechanisms within a purely model checking environment.We have exploited these mechanisms to successfully verify a wide spectrum of large and complex circuits. This paper describes a variety of the decomposition techniques that we have used as part of a large industrial formal verification effort on the Intel Pentium®4 (Willamette) processor.
CITATION STYLE
Beers, R., Ghughal, R., & Aagaard, M. (2001). Applications of hierarchical verification in model checking. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 2144, pp. 40–57). Springer Verlag. https://doi.org/10.1007/3-540-44798-9_3
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