Assessing productivity of high-level design methodologies for high-performance reconfigurable computers

Abstract

In spite of their potential to provide substantial performance improvements over traditional supercomputers, high-performance reconfigurable computers (HPRCs) and their broad acceptance have been hindered by productivity challenges. These challenges arise from increased design complexity, a wide array of custom design languages and tools, and often overblown sales literature. Therefore, it is essential to review, evaluate, and assess the productivity of this technology. This chapter presents a review and taxonomy of high-level languages (HLLs) for HPRCs and a framework for the comparative analysis of their features. It also introduces new metrics and an assessment model based on computational effort. The proposed concepts are inspired by Newton's equations of motion and the notion of work and power in an abstract multidimensional space of design specifications. The metrics are devised to highlight two aspects of the design process: the total time-to-solution and the efficient utilization of user and computing resources at discrete time steps along the development path. The study involves analytical and experimental evaluations demonstrating the applicability of the proposed model.