Computing Goldbach partitions using pseudo-random bit generator operators on an FPGA systolic array

Abstract

Calculating the binary Goldbach partitions for the first 128 × 106 numbers represents weeks of computation with the fastest microprocessors. This paper describes an FPGA systolic implementation for reducing the execution time. High clock frequency is achieved using operators based on pseudo-random bit generator. Experiments carried both on the R10000 processor and on the FPGA PeRLe-1 board are reported.