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Formal Semantics and Proof Techniques for Optimizing VHDL Models

  • Umamageswaran K
  • Pandey S
  • Wilsey P
Springer US, (1999)
DOI: 10.1007/978-1-4615-5123-2
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Umamageswaran, K., Pandey, S. L., & Wilsey, P. A. (1999). Formal Semantics and Proof Techniques for Optimizing VHDL Models. Formal Semantics and Proof Techniques for Optimizing VHDL Models. Springer US. https://doi.org/10.1007/978-1-4615-5123-2

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