Balancing interconnect and computation in a reconfigurable computing array (or, why you don't really want 100% LUT utilization)

Abstract

FPGA users often view the ability of an FPGA to route designs with high LUT (gate) utilization as a feature, leading them to demand high gate utilization from vendors. We present initial evidence from a hierarchical array design showing that high LUT utilization is not directly correlated with efficient silicon usage. Rather, since interconnect resources consume most of the area on these devices (often 80-90%), we can achieve more area efficient designs by allowing some LUTs to go unused - allowing us to use the dominant resource, interconnect, more efficiently. This extends the `Sea-of-gates' philosophy, familiar to mask programmable gate arrays, to FPGAs. Also introduced in this work is an algorithm for `depopulating' the gates in a hierarchical network to match the limited wiring resources.