High performance DFT architectures using winograd fast fourier transform algorithm

Abstract

This paper presents area and latency aware design of Discrete Fourier Transform (DFT) architectures using Winograd Fast Fourier Transform algorithm (WFFT). WFFT is one of the Fast Fourier algorithms which calculate prime sized DFTs. The main component of DFT architectures are Adders and Multipliers. This paper presents DFT architectures using Winograd Fast Fourier Algorithm with Carry Look Ahead Adder and add/shift multiplier and also with Semi-complex Multipliers. In this paper, different prime size DFTs are calculated using polynomial base WFFT as well as conventional algorithm. Area and latency are calculated in Xilinx synthesizer. Polynomial WFFT include Chinese Remainder theorem which increases complexity for higher orders. This paper mainly focuses on prime size 5-point and 7–point WFFT architectures, implemented in Verilog and simulated using Xilinx ISE 13.1. Each sub module is designed using data flow style and finally top level integration is done using structural modeling. DFT architecture has wide range of applications in various domain includes use in Digital Terrestrial/Television Multimedia Broadcasting standard.