A dynamic instruction scratchpad memory for embedded processors managed by hardware

Abstract

This paper proposes a hardware managed instruction scratchpad on the granularity of functions which is designed for real-time systems. It guarantees that every instruction will be fetched from the local, fast and timing predictable scratchpad memory. Thus, a predictable behavior is reached that eases a precise timing analysis of the system. We estimate the hardware resources required to implement the dynamic instruction scratchpad for an FPGA. An evaluation quantifies the impact of our scratchpad on average case performance. It shows that the dynamic instruction scratchpad compared to standard instruction memories has a reasonable performance - while providing predictable behavior and easing timing analysis. © 2011 Springer-Verlag.