FSM-Based VLSI architecture for the 3 × 3 Window-Based DBUTMPF algorithm

Abstract

This paper gives a Novel FSM-based architecture for the decision-based unsymmetrical trimmed midpoint algorithm used for high-density salt and pepper noise (SPN) removal in images. The proposed VLSI architecture uses a FSM-based scheduler for the evaluation of unsymmetrical trimmed midpoint in a fixed 3 × 3 window. The proposed scheduler moves between 4 states of the finite state machine for the evaluation of a suitable value to replace the corrupted value in the decision-based algorithm. The proposed architecture consists of sorting network, FSM scheduler and decision unit, which uses 9 values of the current processing window. This setup acts as a sequential architecture. During the simulation the first output of the decision appears after 16 clock cycles. The proposed architecture was targeted for Xc3e5000-5fg900 FPGA and the proposed architecture occupies 857 slices, consumes 298 MW power, and operates at 98.38 MHz frequency.