Charge-plasma-based super-steep negative capacitance junctionless tunnel field effect transistor: Design and performance

Abstract

A double-gate charge-plasma-based super-steep negative capacitance junctionless tunnel field effect transistor (NC-JLTFET) using a ferroelectric gate stack is proposed. Structurally, the NC-JLTFET consists of a heavily doped n-type silicon (Si) channel with two distinctive gates (control gate and fixed source gate). The fixed source gate accounts for the charge-plasma (hole plasma) formation which results in surrogate p-type doping by using work-function engineering. It induces a uniform p-region on the source side on the n-type doped Si film having a thickness less than the Debye length (LD). The key attribute of the NC-JLTFET is the ferroelectric gate stack which is employed as a control gate resulting in NC behaviour due to positive feedback among the electric dipoles in the ferroelectric material. The NC-JLTFET endeavours to achieve a super-steep sub-threshold slope, a paramount boost in drive current and a substantial enhancement in peak transconductance (gm) than the JLTFET. Meanwhile, it embraces the inherent advantages of the charge-plasma junctionless structure. Thus, it avails itself of a simple fabrication process flow and high immunity against process variations and random dopant fluctuations.