Interconnection delay has become a critical problem in performance improvement of 2D multi-core processors. 3D integration technology can be a good solution for reducing the interconnection delay in multi-core processors. However, the 3D technology magnifies the thermal challenges in multi-core processors. For this reason, the 3D multi-core architecture cannot be practical without proper solutions to the thermal problems. Architecture-level thermal-aware approaches such as dynamic thermal management (DTM) reduce the peak temperature in the processor by sacrificing the performance. On the other hand, thermal-aware design techniques using floorplan lead to peak temperature reduction with minimal performance degradation. This paper investigates how the floorplan schemes handle the thermal problems in 3D multi-core processors. First, we propose two kinds of foorplan schemes for reducing the temperature on integer register and load store queue, respectively. And then, we propose the thermal-aware floorplan schemes by combining these two kinds of floorplan schemes. © 2011 Springer-Verlag.
CITATION STYLE
Son, D. O., Park, Y. J., Ahn, J. W., Park, J. H., Kim, J. M., & Kim, C. H. (2011). Thermal-aware floorplan schemes for reliable 3D multi-core processors. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 6783 LNCS, pp. 463–474). https://doi.org/10.1007/978-3-642-21887-3_36
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