Sublithographic Architecture: Shifting the Responsibility for Perfection

Abstract

In our conventional, top-down, lithographic model we define a minimum lithographically imageable feature size (e.g., half pitch) and build devices that are multiples of this imageable feature size. Within the limits of this feature size, VLSI layout can perfectly specify the size of features and their locations relative to each other in three dimensions — both in the two-dimensional plane of each lithographic layer and with adequate registration between layers. This gives the designer complete flexibility in the layout of circuit structures as long as she adheres to the minimum imageable and repeatable feature size rules.