In this paper, an efficient VLSI architecture of full-search variable block size motion estimation (VBSME) suitable for high quality video is proposed. Memory bandwidth in high-quality video is a mainly responsible for throughput limitations and power consumption in VBSME. The proposed architecture is designed for reducing the memory bandwidth by adopting "meander"-like scan for a high overlapped data of the search area and using onchip memory to reuse the overlapped data. We can reuse the previous candidate block of 98% for the current one and save memory access cycles about 19% in a search range of [-32, +31]. The architecture has been prototyped in Verilog HDL and synthesized by Synopsys Design Compiler with Samsung 0.18um standard cell library. Under a clock frequency of 67MHz, The simulation result shows that the architecture can achieve the real-time processing of 720×576 picture size at 30fps with the search range of [-32∼+31]. © Springer-Verlag Berlin Heidelberg 2007.
CITATION STYLE
Pyen, S. M., Min, K. Y., & Chong, J. W. (2007). An efficient VLSI architecture for full-search variable block size motion estimation in H.264/AVC. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 4352 LNCS, pp. 41–50). https://doi.org/10.1007/978-3-540-69429-8_5
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