Bit synchronization and delayed decision feedback equalization for EDGE BTS - Hardware implementation on TMS320C6424 TI DSP

Abstract

This paper demonstrates the implementation of bit synchronization and delayed decision feedback equalization for Enhanced Data rates for GSM Evolution (EDGE) system on TMS320C6424 DSP. EDGE makes use of training sequence for channel estimation and inter symbol interference (ISI) cancellation by use of delayed decision feedback equalization. Modulated baseband in-phase (I) and quadrature (Q) signals are generated using Agilent E4438C Vector signal generator and faded using Agilent fading simulator, is used as input to the DSP. Bit Error Rate (BER) performance of uncoded bits for Packet Data Traffic Channel (PDTCH) meets the EDGE standards. Software implementation uses fixed-point C and Integrated Development Environment (IDE) used for development is code composer studio (CCS). Prototyped our design in Texas Instrument TMS320C6424 DSP and verified for all propagation models as per the EDGE standards. The design and hardware implementation of this Demodulator is done for C-DOT indigenous Shared GSM Radio Access Network (SGRAN) Base Transceiver Station (BTS) project.