Abstract
This paper describes some recently successful results in the CMOS VLSI implementation of public-key data encryption algorithms. Architectural details, circuits, and prototype test results are presented for RSA encryption and multiplication in the finite field GF(2m). These designs emphasize high throughput and modularity. An asynchronous modulo multiplier is described which permits a significant improvement in RSA encryption throughput relative to previously described synchronous implementations.
Cite
CITATION STYLE
Orton, G. A., Roy, M. P., Scott, P. A., Peppard, L. E., & Tavares, S. E. (1987). VLSI implementation of public-key encryption algorithms. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 263 LNCS, pp. 277–301). Springer Verlag. https://doi.org/10.1007/3-540-47721-7_22
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