Realization of Optimized CORDIC Core for Implementing Sine and Cosine Operations

Abstract

Cordic, which is an iterative vector rotation calculation for different coordination systems, has been proposed in this paper that has low latency and low area utilization. The main limitation is that in comparison to standard CORDIC, the number of micro-rotations necessary increases with the input angle bit-width which leads to additional stages of micro-rotation. In order to overcome this, the most area utilizing stages are recoded using the two bits of the input angle simultaneously such that our suggested technique can achieve a smaller micro-rotation for bigger bit width applications. In this article, using parallel and pipelined CORDIC architecture a Digital sine and cosine generator is intended and applied which utilises optimized Micro-rotation Angle Recoding algorithms to achieve low latency and reduces area of the design. The proposed work reduces the delay by 34%.