A circuit-architecture co-optimization framework for exploring nonvolatile memory hierarchies

Abstract

Many new memory technologies are available in building future energy-efficient memory hierarchies. It is necessary to have a framework that can quickly find the optimal memory technology on each hierarchy level. In this work, we first build a circuit-architecture joint design space exploration framework by combining RC circuit analysis and ANN-based performance modeling. Then, we use this framework to evaluate some emerging nonvolatile memory hierarchies. We demonstrate that an ReRAM-based cache hierarchy on an 8-core CMP system can achieve a 28 % EDP (Energy-Delay Product) improvement and a 39 % EDAP (Energy-Delay-Area Product) improvement compared to a conventional hierarchy with SRAM on-chip caches and DRAM main memory.