Power saving by NoC traffic compression

Abstract

As technology advances, multiprocessor systems-on-chip (MPSoCs) increase with the number of components, relying on an efficient on-chip network (NoC). As the size of the system increases, NoC performance and power consumption become a central issue. In this paper we present compression strategies at the NoC level reducing the number of transmitted flits and consequently the energy consumed. The provided mechanism relies on the abundance of memory data blocks filled with zeros in the analysed applications. We provide a hardware implementation for both compression and decompression at a generic network interface (NI). Results show the effectiveness of the compression and decompression mechanisms and the low overhead they introduce. The percentage of traffic reduced by the compression strategy (factor of 3) justifies the added resources. © 2014 Springer-Verlag Berlin Heidelberg.