The generic neuron architectural framework for the automatic generation of ASICs

Abstract

Artificial neural networks have been mainly implemented as simulations on sequential machines. More recently, the implementation of neurocomputers is being recognised as the way to achieve the real potential of artificial neural networks2. However, current hardware implementations lean either to the optimisation of the network performance, as happens in the case of special-purpose neurocomputers, or to provide more flexibility for the execution of a large range of neural network models, as occurs with the general-purpose neurocomputers. Hence, it is desired to achieve a compromise between these two trends in order to provide high-performance application-specific neurocomputers and, at the same time, allow the user to cost-effectively execute different neural algorithms. This paper reports the results of the VLSI implementation of the so- called generic neuron architecture. This architecture serves as an architectural framework for the automatic generation of applicalion-spccific integrated circuits (ASICs), granting the necessary flexibility and high performance execution.