A new partition lemma for planar graphs and its application to circuit complexity

Abstract

We consider the following combinatorial problem: Given a planar graph. Some of its nodes are labelled by elements of given labelsets Xi, so that each label occurs at most T times. Can we find a “small” vertex set V* and “large” subsets Zi ⊆ Xi, so that after deleting V* none of the remaining connected components contains labels from all sets Zi. Applying this result and the communication complexity model of multiparty protocols we’prove that there are explicitly defined functions fn:={0,1}n → {0, 1} such that any multilective planar Boolean circuit computing fn needs ω(n(logn)2) gates, although these functions can be computed by linear-sized Boolean circuits. This improves the separation of general circuits and multilective planar circuits due to Gy. Turán [7] by a factor of log n.