Abstract
In this paper we introduce our fault tolerant FPGA and explain the fault tolerant features of our FPGA. They result from the block structure, the cell structure, and the intrablock routing along with a global state machine for testing. The state machine along with comparator detects single stuck-at-zero/one faults in the cell structure and mask them on block level.
Cite
CITATION STYLE
Bartzick, T., Henze, M., Kickler, J., & Woska, K. (2000). Design of a fault tolerant FPGA. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 1896, pp. 151–156). Springer Verlag. https://doi.org/10.1007/3-540-44614-1_16
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